This invention relates to a method for accessing a dynamic random-access memory.
A conventional method for accessing dynamic random-access memories (hereinafter sometimes abbreviated as "DRAM") is shown in FIG. 7. In response to the falling of a row address strobe (RAS) signal, an upper address is sent to the DRAM for accessing it. On the other hand, in response to the falling of a column address strobe (CAS) signal, a lower address is sent to the DRAM for addressing it.
During the read/write mode of DRAM, the above-described timing is repeated to access the DRAM so that desired data can be written into or read from the DRAM.
In order to access the DRAM from a central processing unit (CPU) by the conventional access method described above, respective signals must be sent out for each access in accordance with the timing specified above. With a high-speed 32-bit CPU, a wait time of several cycles is necessary and this inevitably increases the access time.
The clock rate of recent models of CPU is very high and in order to cope with this situation, a cache memory is often composed using an expensive static RAM. However, a large-capacity memory composed of a static RAM is expensive and, at the same time, the cache memory requires a complicated control circuit.